library verilog;
use verilog.vl_types.all;
entity ext is
    port(
        immd            : in     vl_logic_vector(10 downto 0);
        mode            : in     vl_logic_vector(2 downto 0);
        immd16          : out    vl_logic_vector(15 downto 0)
    );
end ext;
